This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-258009, filed Sep. 10, 1999; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a microprocessor having a function of a clock supply halt mode, and, more particularly, to a microprocessor such as a RISC processor and the like capable of reducing a power consumption.
2. Description of the Related Art
In particularly, a microprocessor such as a RISC processor is widely incorporated in a mobile information station, for example, such as a mobile phone, because the RISC processor is a device of a low power consumption type. Such a microprocessor of a low power consumption type has and also executes an instruction to enter a sleep mode or a standby mode in which the supply of an internal clock to a processor core is temporarily halted in order to reduce the power consumption.
FIG. 7 is a block diagram showing a configuration of a conventional microprocessor having the clock supply halt mode.
In the conventional microprocessor having the configuration shown in FIG. 7, a processor core 1 executes a clock supply halt instruction and provides an instruction to the clock supply halt control section 2 in order to halt the supply of the clock. When receiving the instruction from the processor core 1, the clock supply halt control section 2 sets a value xe2x80x9c1xe2x80x9d to the flip-flop (F/F) 3. Then, an OR circuit 4 outputs a fixed value xe2x80x9c1xe2x80x9d, and no clock CLK is thereby supplied to the processor core 1. Therefore the processor core 1 enters a clock supply halt mode so that the power consumption of the microprocessor can be reduced.
Next, a description will be given of a case in which an exception request happens while the processor core 1 is executing the clock supply halt instruction Z.
FIG. 8 is a flowchart showing the operation of the processor core in the conventional microprocessor when the exception request happens.
At first, when receiving the exception request from outside, the exception request detection circuit 5 detects this request (Step S801) and then provides an instruction to release the clock supply halt mode to the clock supply halt control section 2. When receiving the instruction from the exception request detection section 5, the clock supply halt control section 2 resets the flip-flop 3, namely, sets the value xe2x80x9c0xe2x80x9d to the flip-flop 3. Thereby, the clock CLK is supplied to the processor core 1 through the OR circuit 4 because the OR circuit 4 inputs both the output value xe2x80x9c1xe2x80x9d from the flip-flop 3 and the clock CLK. The processor core 1 or another control circuit (not shown) sets to a program counter (hereinafter referred to as PC) a following address of an instruction whose address is next to the address of the clock supply halt instruction Z which is executed by the processor core 1 when this exception request happens (Step S802).
Because the supply of the clock CLK to the processor core 1 is restarted through the OR circuit 4, the processor core 1 is switched from the clock supply halt mode to a normal operation mode, and the processor core 1 then executes an exception handling routine based on the exception handling instruction (Step S803).
When the execution of the exception handling routine is completed, the processor core 1 returns from the exception handling routine and then executes the following instruction that is next to the clock supply halt instruction Z.
FIGS. 9A and 9B are diagrams showing an instruction sequence and an operation procedure, respectively, to be executed when the exception request shown in the flow chart of FIG. 8 happens. FIG. 9A and FIG. 9B each shows the occurrence of the exception request and the instruction C to be executed by the processor core 1 after the return form the exception handling routine in a time sequence.
As shown in both FIG. 9A and FIG. 9B, the instruction to be executed by the processor core 1 immediately following the completion of the exception handling routine is the instruction C in a case where the exception request happens during the execution of the clock supply halt instruction Z.
In an actual process of the conventional microprocessor having the clock supply halt mode, however, the microprocessor normally enters the standby mode during the clock supply halt mode and then executes the exception handling routine when an event of the exception handling happens by interrupt, and the microprocessor returns to the clock supply halt mode after the completion of the exception handling routine. In this case, it is necessary to execute the clock supply halt instruction Z after the completion of the exception handling routine caused by the interrupt in order to shift the microprocessor having the conventional configuration from the exception handling mode to the clock supply halt mode. Because in the microprocessors having many conventional configurations, the instruction to be executed immediately following the completion of the exception handling routine is the following instruction, namely, the instruction C shown in FIG. 9(a) whose address is next to the address of the instruction that was executed when the exception request happened.
In order to solve this conventional problem, it is possible to have a configuration in which the clock supply halt instruction Z (which was executed when the exception request happens) is forcedly set to be executed after the return from the execution of the exception handling routine only when the interrupt happened during the execution of the clock supply halt instruction Z.
However, there are many kinds of actual interrupts, for example, a timer interrupt, and there is an actual case in which the instruction to be executed immediately following the completion of the exception handling routine for the timer interrupt is an instruction other than the clock supply halt instruction under the condition in which the microprocessor was in the clock halt mode when the timer interrupt happened.
As described above, although the conventional microprocessor having the clock supply halt mode returns only to a fixed mode such as the clock supply halt mode immediately following the completion of the exception handling routine caused by the interrupt happened during the clock supply halt mode, it is difficult to return any desired modes other than the clock supply halt mode. That is, the microprocessor having the conventional configuration described above cannot return to any actual desired modes.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a microprocessor capable of returning to a desired mode based on information regarding which instruction is executed by a processor core when an exception request caused by an interrupt and the like happened under the execution of the clock supply halt instruction, and also capable of reducing a power consumption.
In accordance with a preferred embodiment of the present invention, a microprocessor is capable of handling a function for setting a processor core into a standby state caused by executing a clock supply halt instruction in which a supply of a clock to the processor core for executing various kinds of processes and instructions is temporarily halted. In particularly, the microprocessor comprises a memory circuit for storing a state of the processor core at an occurrence time of an exception request caused by an interrupt. In the above microprocessor, the processor core selects and executes the instruction to be executed according to the value stored in the memory circuit when the state of the processor core returns from an exception handling after a completion of the exception handling caused by the exception request.
In the microprocessor as another preferred embodiment of the present invention, the memory circuit stores the value to be used for judging whether the processor core is in the standby state in which no clock is supplied or in a normal state other than the standby state when the exception request happens.
In the microprocessor as another preferred embodiment of the present invention, the value stored in the memory circuit indicates that the processor core is in the standby state where no clock is supplied when the exception handling happens, the processor core selects the clock supply halt instruction to be executed when the state of the processor core returns from the exception handling after the completion of the exception handling.
In the microprocessor as another preferred embodiment of the present invention, the value stored in the memory circuit indicates that the processor core is in the standby state where no clock is supplied when the exception handling happens, the processor core selects an instruction, whose address is next to the address of the clock supply halt instruction, to be executed when the state of the processor core returns from the exception handling after the completion of the exception handling.
In the microprocessor as another preferred embodiment of the present invention, the value stored in the memory circuit indicates that the processor core is in the normal state other than the standby state where no clock is supplied when the exception handling happens, the processor core selects an instruction, whose address is next to the address of the clock supply halt instruction, to be executed when the state of the processor core returns from the exception handling after the completion of the exception handling.
In the microprocessor as another preferred embodiment of the present invention, the memory circuit is a flip-flop for storing a value indicating whether the clock is supplied to the processor core or not, and the processor core checks the value stored in the flip-flop until the exception handling is completed in order to judge whether the state of the processor core when the exception handling happens is in the standby state where no clock is supplied or in a normal state other than the standby state.
In the microprocessor as another preferred embodiment of the present invention, the processor core changes the instruction to be executed when the state of the processor core returns from the exception handling after the completion of the exception handling.
In accordance with another preferred embodiment of the present invention, a microprocessor is capable of handling a function for setting a processor core into a standby state caused by executing a clock supply halt instruction in which a supply of a clock to the processor core for executing various kinds of processes and instructions is temporarily halted. In particularly, the microprocessor comprises a logical circuit, a first memory circuit, a second memory circuit, and a judgment control section. The logical circuit performs a supply/halt of the clock to the processor core. The first memory circuit stores a set value to be used for controlling the supply of the clock to the processor core through the logical circuit. The second memory circuit stores the set value of the first memory circuit. The judgment control section sets the set value of the first memory circuit to the second memory circuit at an occurrence time of the exception request when the judgment control section detects the occurrence of an exception request, in order to supply the clock through the logical circuit to the processor core, and indicates that the processor core executes the exception handling. In the microprocessor, the processor core sets the instruction to be executed according to the set value of the second memory circuit when the processor core returns from the exception handling after the completion of the exception handling.
In the microprocessor as another preferred embodiment of the present invention, the judgment control section comprises an exception request detection section, and a clock supply halt control section. In the microprocessor, the exception request detection section detects an occurrence of the exception request and outputs a detection result to both the clock supply halt control section and the processor core. The clock supply halt control section sets the set value of the first memory circuit to the second memory circuit according to the detection result from the exception request detection section. The processor core executes the exception handling based on the detection result from the exception request detection circuit, and controls the setting operation to the first memory circuit by the clock supply halt control section based on the set value of the second memory circuit after the completion of the exception handling, and selects and executes the instruction to be executed after the completion of the exception handling.
In the microprocessor as another preferred embodiment of the present invention, each of the first memory circuit and the second memory circuit is a flip-flop.
In the microprocessor as another preferred embodiment of the present invention, the logical circuit is an OR gate which inputs the clock as one input and inputs the set value of the first memory circuit as another input.
In the microprocessor as another preferred embodiment of the present invention, the logical circuit is an AND gate which inputs the clock as one input and inputs the set value of the first memory circuit as another input.